The fabrication of structures associated with semiconductor substrates (e.g., fabrication of integrated circuitry, fabrication of micro-electro-mechanical systems, etc.) may include process stages in which numerous openings of different sizes and depths are to be filled with dielectric material. Subsequently, planarization (e.g., chemical-mechanical polishing) may be utilized to attempt to form a planar surface which extends across the dielectric material within the openings, and across regions of the semiconductor substrate between the openings. However, difficulties are encountered with conventional processes, as described with reference to FIGS. 1-3.
FIG. 1 shows a construction 10 which includes a semiconductor substrate 12. The semiconductor substrate 12 includes semiconductor material; and may, for example, comprise, consist essentially of, or consist of monocrystalline silicon. The term “semiconductor substrate” (or alternatively, “semiconductor construction”) means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some applications, the semiconductor substrate 12 may contain one or more materials associated with integrated circuit fabrication, and/or one or more materials associated with the fabrication of micro-electro-mechanical systems (MEMS). Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.
Openings 14, 16 and 18 are shown extending into the semiconductor substrate 12, with the openings having different sizes relative to one another. In some applications, the substrate 12 and be considered to have an upper surface 19, and the openings 14, 16 and 18 may be considered to extend through such upper surface and into the underlying substrate. In some applications, the upper surface 19 may be a substantially planar upper surface; with the term “substantially planar” meaning planar to within reasonable tolerances of fabrication and measurement.
Although the substrate 12 is illustrated to be homogeneous, in some embodiments the substrate may comprise multiple materials, structures, components, etc. associated with integrated circuit fabrication and/or MEMS fabrication. For instance, in some embodiments the substrate 12 may include a semiconductor material wafer (for instance, a monocrystalline silicon wafer) supporting wordlines, bitlines and memory cells of a memory array (for instance, a three-dimensional NAND memory array), and supporting circuitry peripheral to the memory array.
The openings 14, 16 and 18 may be representative of a large number of openings which extend into the substrate 12 after fabrication of components associated with integrated circuitry and/or MEMS.
The opening 14 may be along the edge of a wafer and may correspond to, for example, an alignment mark utilized for aligning the wafer during masking and/or other process stages.
The opening 16 may correspond to, for example, an opening extending to a staircase region adjacent integrated memory. For instance, the integrated memory may correspond to three-dimensional NAND and/or other three-dimensional memory, and the staircase region may be a region where contacts are formed to bitlines and/or wordlines associated with the three-dimensional memory. The bottom of opening 16 is shown to comprise tiers (i.e., steps), and accordingly opening 16 is an example of an opening having a non-planar bottom surface. In contrast, openings 14 and 18 are examples of openings having planar bottom surfaces. In some aspects, the steps at the bottom of opening 16 may be considered to be representative of stair-step type structures.
The opening 18 may correspond to, for example, of an opening remaining within a memory array region, or other region, during fabrication of integrated circuitry and/or MEMS.
Openings may have shapes other than those shown for openings 14, 16 and 18; and may, for example, have tapered conical shapes, non-straight sidewalls, etc.
Referring to FIG. 2, dielectric material 20 is formed across the upper surface 19 and within the openings 14, 16 and 18. The dielectric material 20 may be spin-on dielectric, and in some applications may comprise silicon oxide.
Ultimately, excess dielectric material 20 is to be removed to leave a planar surface (as described below with reference to FIG. 3). The excess dielectric material 20 may be referred to as overburden. The variation in sizes amongst the openings 14, 16 and 18 leads to a substantial variation in the thickness of the overburden of dielectric material 20. Specifically, the overburden across opening 16 is less than the overburden across upper surface 19, or the overburden across openings 14 and 18.
Referring to FIG. 3, construction 10 is shown after planarization (for instance, chemical-mechanical polishing) to remove the overburden of dielectric material 20. Ideally, such forms a planarized surface 21. However, the substantial overburden and non-uniformity of the thickness of the overburden (shown in FIG. 2) may lead to difficulties during the planarization process; and may result in dishing and/or other structural defects rather than the desired planar surface 21. For instance, a concave (or dished) surface 21a (shown with a dashed line) may result rather than the desired planar surface 21.
Another problem that may occur relative to the prior art processing of FIGS. 2 and 3 is that the large amount of dielectric material 20 within opening 16 may experience substantial shrinkage and/or other strain-inducing characteristics during subsequent thermal treatments, which may lead to cracks forming in the material 20 and/or in regions adjacent to the material 20.
It is desired to develop improved fabrication methods which alleviate the problems described above with reference to FIGS. 2 and 3.